ROOT ▮ ENERGY-EFFICIENT AI BRANCH_1 OF ONE SPINE
TRACK 02 — FOR SAMSUNG · SK FOLKS
Compute belongs
inside memory.
The memory wall is the whole game for AI silicon. I've attacked it from three sides: RRAM-based compute-in-memory, dynamic adaptive on-chip memory management, and buffer-minimal accelerator dataflows — with two Samsung 28nm tape-outs along the way.
WHY ME FOR THIS TRACK
I've fabricated compute-in-memory
SNN-based CIM MPW with RRAM synaptic circuits — PSpice-modeled neurons, fabricated synapse arrays, real measurements.
Memory hierarchy is my optimization target
S³A-NPU's headline contribution is dynamic adaptive memory optimization — published in IEEE TVLSI 2025.
Two Samsung 28nm tape-outs
HAB-1 (2024) and the sparsity transformer accelerator (2025) — I know the Samsung foundry flow from RTL to GDS.
EVIDENCE
SNN-based Compute-In-Memory with RRAM Synapses
Neuromorphic CIM architecture, PSpice neuron simulation, fabricated synaptic circuits
S³A-NPU — Dynamic Adaptive Memory Optimization
On-chip memory management tuned at runtime to spiking SSL workload phases
Samsung 28nm Tape-outs — HAB-1 & Transformer Accelerator
Host-accelerator bridge with multi-channel MPI; sparsity-aware datapaths with MMIO control
Buffer Memory Reduction for Lane Detection on FPGA
Sliding-based parallel segment detection that cuts line-buffer requirements
Let's break the
memory wall together.
OPEN TO RESEARCH INTERNSHIPS — PIM / CIM / MEMORY SYSTEMS TEAMS