heuijee.yun CV
4 TAPE-OUTS · GROUPED BY BRANCH · LIVE DEMOS

Projects

Real silicon, sorted by the same three branches. Don't just read them — every project has a live interactive demo.

BRANCH_0

Core & Accelerator

→ FOCUS-CORE └─ cores & accelerators that shipped to silicon
2025 · SAMSUNG 28nm TAPE-OUT

RISC-V Adaptive Clock Control + Sparsity-Aware Transformer Accelerator

Chip layout
LIVE DEMO

Dark cells are zero weights — the accelerator skips them and the RISC-V controller gates the clock down. Drag the slider and watch the power drop.

RISC-V controller tunes clock gating in real time using sparsity and queue depth.

Accelerator supports weight sparsity and zero-skip paths with MMIO controls.

Achieves strict latency with deterministic dense-fallback and policy logging.

RISC-VTransformerSparsityClock Gating28nm ASIC
2023 · SK KEYFOUNDRY 130nm TAPE-OUT

ARMuP — Cortex-M0+ Compatible Core with µSIMD

ARMuP chip
LIVE DEMO

Same MAC workload, two cores: plain scalar Cortex-M0+ vs. ARMuP with custom µSIMD instructions crunching 4 elements per cycle.

Custom ISA compatible with Arm Cortex-M0+.

Custom µSIMD instruction support for enhanced performance.

Scalable memory & tile-SoC interface for accelerator control.

Cortex-M0+Custom ISAµSIMD130nm ASIC
BRANCH_1

Memory & CIM

→ FOCUS-MEMORY └─ data movement & compute-in-memory
2024 · SAMSUNG 28nm TAPE-OUT

HAB-1 — Reconfigurable Host-Accelerator Bridge

HAB-1 chip
LIVE DEMO

Packets stream from the host CPU through the reconfigurable bridge into the CNN accelerator. Reconfigure the MPI channels and watch throughput scale.

Reconfigurable bridge for host–accelerator communication.

Scalable multi-channel MPI interface for accelerator control.

Reconfigurable CNN accelerator for adaptive AI workloads.

SoC BridgeMulti-Channel MPICNN Accelerator28nm ASIC
2023 · MPW TAPE-OUT

SNN-based Compute-In-Memory (CIM)

SNN CIM chip
LIVE DEMO

Input spikes flow through an RRAM crossbar; each output neuron integrates charge until its membrane potential crosses threshold — then it fires. Click the canvas to stimulate.

SNN-based compute-in-memory architecture for energy-efficient neuromorphic computing.

PSpice-based SNN neuron circuit simulation for accurate synaptic behavior modeling.

RRAM-based synaptic circuit fabrication for low-power AI acceleration.

SNNCompute-In-MemoryRRAMNeuromorphic
BRANCH_2

Autonomous Driving

→ FOCUS-AUTO └─ perception, validated before the road
2020 · DIGITAL TWIN

Autonomous Vehicle Simulation with GTA5

GTA5 simulation
LIVE DEMO

A miniature version of the pipeline: Canny-style lane detection plus YOLO-style bounding boxes running over a moving road scene.

Digital-twin simulation for autonomous driving using the GTA5 game engine.

Real-time object detection and avoidance with OpenCV, YOLOv4, and TensorFlow.

Lane detection and tracking using Canny edge detection for vehicle navigation.

Digital TwinYOLOv4OpenCVLane Detection