Heuijee
Yun
PH.D. STUDENT · AI HARDWARE / SOC DESIGN
Profile
Ph.D. student designing low-power AI accelerators — from spiking neural network architectures and self-supervised learning down to tape-out. Four chip tape-outs (Samsung 28nm ×2, SK keyfoundry 130nm, MPW), 16+ peer-reviewed publications including IEEE TVLSI and DAC. Also builds custom PCBs, 3D-printed devices, and self-hosted AI systems for fun.
Education
Ph.D. Student, Electronics and Electrical Engineering
Kyungpook National University · AI-S²oC Lab · Advisor: Prof. Daejin Park
B.S. in Electronics Engineering
Kyungpook National University
Chip Tape-outs
RISC-V Adaptive Clock Control + Sparsity-Aware Transformer Accelerator
Samsung 28nm — zero-skip datapaths, runtime clock gating via RISC-V controller, MMIO control
HAB-1 — Reconfigurable Host-Accelerator Bridge
Samsung 28nm — multi-channel MPI interface, reconfigurable CNN accelerator
ARMuP — Cortex-M0+ Compatible Core with Custom µSIMD
SK keyfoundry 130nm — custom ISA, µSIMD instructions, tile-SoC memory interface
SNN-based Compute-In-Memory
RRAM synaptic circuits, PSpice neuron modeling, neuromorphic architecture
Selected Publications (6 J / 10 C total)
→ full list at heuijee.github.io/publications
Skills
Awards
KNU-EE Funded Excellence Ph.D. Award
10,000,000 KRW scholarship