heuijee.yun CV
Heuijee Yun

Heuijee Yun

PH.D. RESEARCHER · AI-S²OC LAB · KNU

From frontend
to silicon.

I take AI down the whole stack — perception, model, architecture, memory, silicon. One obsession: efficient intelligence.

drag · click a layer

How do you make AI efficient enough to run everywhere — from the car's cockpit to the last transistor?

01

APPLICATION

Perception that keeps a car safe.

Camera + LiDAR + thermal fusion — so a vehicle sees what a camera alone can't, on hardware that fits in the car.

83.9%pedestrian detection
up from 40.4%
2.7fpsreal-time on
Jetson Nano
Thermal-RGB fusionLiDAR + 2DLane detectionGTA5 digital twin
PerCom · IEEE Access · Sensors HyundaiTesla
02

MODEL & SOFTWARE

Learning that costs almost nothing.

Spiking neural networks meet self-supervised learning — plus the compiler that turns a model into tuned hardware code, automatically.

1stcomprehensive SNN-SSL
hardware framework
FPGA+ASICauto-generated
from one model
Spiking NNSelf-supervisedPruningQuantizationTVM codegen
DAC · IEMEK · MWSCAS NVIDIAETRI
03

ARCHITECTURE

Cores & accelerators, designed — not just used.

I design the datapath and the control: a spiking NPU, a RISC-V clock controller, a custom Cortex-M0+ core with my own µSIMD.

4×MAC throughput
via custom µSIMD
IEEETVLSIS³A-NPU
journal paper
Spiking NPURISC-V controlCustom ISA / µSIMDSparsity zero-skip
TVLSI · COOLChips · custom ISA ArmAMDNVIDIA
04

MEMORY & CIM

Win at the memory wall.

Moving data costs the most energy — so I attack it directly: on-chip memory that adapts in real time, and compute done inside the memory with RRAM.

RRAMcompute-in-memory
fabricated (MPW)
runtimeadaptive on-chip
memory allocation
Compute-in-memoryAdaptive on-chip memBuffer minimization
RRAM CIM tape-out · IEEE Access · ICCE SamsungSK hynix
05

SILICON

It's not real until it's fabricated.

Every idea above ends here — a taped-out chip, a hand-routed PCB, a physical device. RTL to GDS.

4chip
tape-outs
3process nodes
28nm · 130nm · MPW
RTL → GDSSamsung 28nm ×2SK 130nmCustom PCB3D printing
Full ASIC flow · home lab Every silicon team
0+Publications
incl. IEEE TVLSI, DAC
0Chip tape-outs
28nm ×2 · 130nm · MPW
0+Years of research
algorithm → silicon
0Layers of the stack
end to end

Go deeper

Whether you design cores, stack memory, drive autonomy, or fund the research

one researcher, the whole stack, all the way to silicon.